Excerpt from a June 2015 contributed post to Planet Analog.
Neal Baltz, Analog and Mixed-Signal IC Design Engineer, Cactus Semiconductor, Inc.
The Planet Analog post by Paul Illegems, “Can You Easily Build Integrated Power Switches? Part 2,” offers sound design principles to limit switch Rds_on and parasitic routing resistance when building integrated power switches. Following up with circuit verification is an important step to ensure design integrity through parasitic extraction and final simulations. Understanding and making the most of these tools to model parasitic metal and VIA resistance is important. It allows a designer to verify that a power switch will meet or exceed its design specification.
Power switches are often distributed into arrays of device fingers and VIAs with large metal routes to limit metal resistance. It may not be uncommon for this routing to include millions of VIAs spread throughout a number of metal layers. This can make it a challenge to develop a back-of-the-envelope simplified resistance model. Combining parasitic extraction and simulation tools harness a powerful means to model these parasitics. A designer should be cognizant that modeling accuracy is often compromised with the speed of parasitic extraction and simulation time. With the following recommendations, a designer may have a greater level of confidence in the accuracy of circuit verification for an integrated power switch.
Parasitic Extraction Tools
When utilizing a parasitic extraction tool to model routing resistance, a variety of VIA reduction techniques are offered to limit the size and complexity of its parasitic netlist. Care must be taken with the extraction tool not to oversimplify the equivalent parasitic circuit. For instance, consider the basic metal and VIA array network resistance from Point A to Point B in Figure 1:
The equivalent resistance from Point A to Point B in Figure 1 is 10 Ω . However, default VIA reduction techniques offered with parasitic extraction tools may combine these parallel VIAs into a “SuperVIA” located at the midpoint in the array. This VIA reduction technique illustrated in Figure 2 results in an equivalent resistance of 15 Ω:
The basic VIA reduction example of Figure 2 yields a 50% difference in equivalent resistance compared to the actual network resistance of Figure 1. A designer must understand and carefully weigh the tradeoffs between accuracy and size of an equivalent parasitic netlist. Continue reading and see the related figures.