A March 2015 post contributed to Planet Analog:
Erik Mentze, Sr. IC Design Engineer, Cactus Semiconductor
In our previous post Low Power LDO Design Techniques for Really Small Profile Applications, Part 1 , we reviewed LDO design tradeoffs using an NMOS pass transistor. This design approach is proven good to implement on next generation really small-profile applications. In particular, this includes applications where the unregulated power supply voltage (Vsply) is much greater than the regulated output voltage (Vreg). Example applications include miniature implantable medical devices, Internet-of-Things devices and more. Here, a simple NMOS pass transistor architecture is often the best choice. However, in applications where Vreg approaches Vsply, a PMOS LDO architecture is often required.
As referenced in Figure 2 below, there are several differences between the PMOS and NMOS LDO architecture. The focus here will be on the pole position P1 and P2. The dominant pole is now required to be at the output of the LDO, with the secondary pole at the pass transistor (MP) gate. While on the surface this seems like a small difference, it actually has very large implications to error amplifier design. We are no longer able to achieve high loop gain and low dominant pole frequency simply by increasing ro.
LDO block diagram with PMOS pass transistor.
The question to ask is why are we not able to set the pole on the gate of MP as the dominant pole? From a pure frequency stability stand point (that is, not thinking about circuit function but only system stability) this is perfectly fine. However, we should look at what is happening on the pass transistor gate from an AC perspective. If so, we see that an AC ground is formed on this node as the error amplifier’s gain rolls off. For an NMOS pass device this turns MN off at high frequency, exactly what we want, from a PSRR perspective. For a PMOS pass device this AC ground turns MP on at high frequency. This potentially creates a case where supply noise is no longer attenuated but, instead gained up (think of it as a common-gate amplifier). Since this is a highly undesirable operating condition, the two poles must be set as shown in Figure 2. Read the rest on PlanetAnalog.com.